SI9712 vishay siliconix document number: 70024 s-40755?rev. f, 19-apr-04 www.vishay.com 1 pc card (pcmcia) interface switch?12-v suspend capability features programmable v cc ramp smart switching 12-v sleepmode compatible extremely low r on reverse blocking switches v pp programmable to 0, 12-v or v cc safe power-up low power consumption pc card 3-v/5-v compatible logic compatible inputs single so-16 package description the SI9712 combines low on-resistance with slow ramp time and smart switching for overall best performance in integrated pc card interface switches. the SI9712 operates off the 5-v supply and has built-in level shifting for gate drive. internal logic protects against an external control input error that would short 5 v to the 3.3-v supply. this protection logic also allows the SI9712 to be configured for positive or negative control logic for compatibility with a variety of pc card controllers. these control inputs are cmos logic compatible and can be driven to 3.3 v or 5 v. the SI9712 complies with the release of the pc card standard by suppling 0 v, 12 v, and v cc to the v pp output and 0 v, 3.3 v, and 5 v to the v cc output. the v cc ramp time is user programmable with an external capacitor connected to the sr pin. the pc card switch is packaged in a narrow body so-16 package and is rated over the industrial temperature range ? 40 to 85 c. the SI9712 is available in both standard and lead (pb)-free packages. functional block diagram +12 v in +5 v in +3.3 v in s 1 s 2 v pp v cc v cc s 4 s 3 gnd switch logic, level shift, and drivers sw 1 sw 2 sw 3 sw 4 v pp (14) (12) (10) (3) (4) (5) (7) (2) (15) (1) sw 5 (8) (9) (16) sr sw 6 (11) (6) v cc +3.3 v in v cc (13) externally connect on pcb
SI9712 vishay siliconix www.vishay.com 2 document number: 70024 s-40755?rev. f, 19-apr-04 absolute maximum ratings voltages referenced to ground +12 v in 15 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +5 v in 7 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +3.3 v in c 7 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . s 1 through s 4 (cmos inputs) 7 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . i out v pp a 300 ma . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . all pins ? 0.5 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . i out v cc b 4 a . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . pd max: (t a = 25 c) 2.5 w . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (t a = 85 c) 1.0 w . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . junction temperature 125 c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . thermal rating?r ja 40 c/w . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . notes a. pins 3, 4 connected together externally. b. pins 5, 6, 7, 13 connected together externally. c. pins 10, 11 connected together externally. recommended operating conditions +12 v in 0 or 12 v 10% . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +5 v in (must be present) 5 v 10% . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +3.3 v in c 3.3 v 10% . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . c sr 33 nf . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . i out v pp a 150 ma . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . i out v cc b 2 a . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . v pp load capacitance 10 f max . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . v cc load capacitance 150 f max . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . notes a. pins 3, 4 connected together externally. b. pins 5, 6, 7, 13 connected together externally. c. pins 10, 11 connected together externally. specifications test conditions unless otherwise specified limits ? 40 to 85 c parameter symbol c sr = 33 nf, +12 v in = 12 v, +5 v in = 5 v +3.3 v in = 3.3 v, low 0.8 v, high 2.2 v min a typ b max a unit switch 1 on resistance r on i = 120 ma, +12 v in = 11.4 v s 3 = s 1 = high t a = 25 c 120 m on-resistance r on s 3 = s 1 = high s 2 = s 4 = low t a = 85 c 145 m off current (+12 v in ) i off +12 v in = 12.6 v t a = 25 c 1 a off current (+12 v in ) i off +12 v in = 12 . 6 v s 1 = low t a = 85 c 10 a switching time t sw1(on) s 2 = s 4 = low, see fi g ure 1 50 200 350 s switching time t sw1(off) s 2 = s 4 = low , see figure 1 s 3 = high 1.0 10 s delay time t d(on) see fi g ure 3 1.0 6 20 ms delay time t d(off) see figure 3 s 2 = s 4 = low 0.1 2.9 10 s rise time t sw1(on) s 2 = s 4 = low, s 3 = high, see figure 2 50 150 300 s switch 2 on resistance r on i = 120 ma, s 2 = s 3 = hi g h t a = 25 c 150 m on-resistance r on i = 120 ma , s 2 = s 3 = high s 1 = s 4 = low t a = 85 c 180 m switching time t sw2(on) s = s = low s = high see figure 1 50 200 350 s switching time t sw2(off) s 1 = s 4 = low, s 3 = high , see figure 1 1.0 10 s delay time t d(on) s = s = low see figure 3 1.0 6 20 ms delay time t d(off) s 1 = s 4 = low, see figure 3 0.1 1.7 10 s rise time t sw2(on) s 1 = s 4 = low, s 3 = high, see figure 2 50 150 300 s switch 3 on resistance r on i = 500 ma, s 3 = hi g h t a = 25 c 70 m on-resistance r on i = 500 ma , s 3 = high s 1 = s 2 = s 4 = low t a = 85 c 95 m off current (v cc ) i off +5 v in = 5.5 v, v cc = 0 v s 1 = s 2 = s 3 = low t a = 25 c 1 a off current (v cc ) i off s 1 = s 2 = s 3 = low s 4 = high +3.3 v in = open circuit t a = 85 c 10 a rise time t sw3(on) s 1 = s 2 = s 4 = low see figure 2 0.1 1.7 10 ms fall time t sw3(off) s 1 = s 2 = s 4 = low, see figure 2 3 30 50 ms
SI9712 vishay siliconix document number: 70024 s-40755?rev. f, 19-apr-04 www.vishay.com 3 specifications limits ? 40 to 85 c test conditions unless otherwise specified c sr = 33 nf, +12 v in = 12 v, +5 v in = 5 v +3.3 v in = 3.3 v, low 0.8 v, high 2.2 v parameter unit max a typ b min a test conditions unless otherwise specified c sr = 33 nf, +12 v in = 12 v, +5 v in = 5 v +3.3 v in = 3.3 v, low 0.8 v, high 2.2 v symbol switch 4 on resistance r on i = 500 ma, s 4 = hi g h t a = 25 c 50 m on-resistance r on i = 500 ma , s 4 = high s 1 = s 2 = s 3 = low t a = 85 c 70 m off current (+3 3 v in ) i off +3.3 v in = 3.6 v, t a = 25 c 1 a off current (+3.3 v in ) i off +3 . 3 v in = 3 . 6 v , s 1 = s 2 = s 3 = s 4 = low t a = 85 c 10 a rise time t sw4(on) s 1 = s 2 = s 3 = low see figure 2 0.1 0.9 10 ms fall time t sw4(off) s 1 = s 2 = s 3 = low, see figure 2 3 20 40 ms switch 5 on resistance r on i = 2 ma s 1 = s 2 = low t a = 25 c 235 400 on-resistance r on i = 2 ma, s 1 = s 2 = low t a = 85 c 325 550 switch 6 on resistance r on i = 2 ma s 3 = s 4 = low t a = 25 c 140 400 on-resistance r on i = 2 ma, s 3 = s 4 = low t a = 85 c 200 500 power supply +5 v in current input (on) i +5vin(1) s 1 = s 4 = 0 v , s 2 = s 3 = 3 v 20 50 +5 v in current input (on) i +5vin(2) s 1 = s 4 = 3 v , s 2 = s 3 = 0v 20 50 a +5 v in current input (off) i +5vin(3) s 1 = s 2 = s 3 = s 4 = 0 v <1 10 switch control inputs input v oltage high v i(h) +5 v in = 5.5 v 2.2 1.8 input voltage high v i(h) +5 v in = 4.5 v 2.2 1.6 v input voltage low v i(l) +5 v in = 5.5 v 1.6 0.8 v input voltage low v i(l) +5 v in = 4.5 v 1.4 0.8 input current high i i(h) s 1 through s 4 = 5 v 1.0 a input current low i i(l) s 1 through s 4 = gnd ? 1.0 a notes a. the algebraic convention whereby the most negative value is a minimum and the most positive a maximum. b. typical values are for design aid only, not guaranteed nor subject to production testing.
13 gnd +3.3 v in s 4 +3.3 v in v pp +5 v in v pp s 2 v cc v cc v cc v cc +12 v in s 3 s 1 sr so-16 14 15 16 2 3 4 1 10 11 12 5 6 7 9 8 top view note: pins 5, 6, 7, and 13 must be connected in the pcb for correct operation. SI9712 SI9712 vishay siliconix www.vishay.com 4 document number: 70024 s-40755?rev. f, 19-apr-04 timing waveforms figure 1. v pp switch delay 3 v s x 50% 90% gnd gnd t d(off) t d(on) 3 v s x 90% gnd gnd t sx(off) t sx(on) figure 2. switch ramp 10% figure 3. delay from s 1 or s 2 to v pp power-up s 3 v pp t d(off) t d(on) v cc s 1 or s 2 50% 50% 50% sw x v pp sw x pin configuration and description pin number function description 1. gnd ground connection. 2 s 4 control input for selecting +3.3 v in to v cc . the pc card terminology for this pin is v cc _en 0 . 3, 4 v pp program and peripheral voltage to pc card slot. 5, 6, 7, 13 v cc supply voltage to slot. 8 s 1 control input for selecting +12 v in to v pp . the pc card terminology for this pin is v pp _en 1 . 9 s 2 control input for selecting v cc to v pp . the pc card terminology for this pin is v pp _en 0 . 10, 11 +3.3 v in +3.3-v supply. 12 +5 v in +5-v supply. 14 +12 v in +12-v supply. 15 s 3 control input for selecting +5 v in to v cc . the pc card terminology for this pin is v cc _en 1 . 16 sr slew rate control pin, capacitor to gnd defines programmable ramp time.
SI9712 vishay siliconix document number: 70024 s-40755?rev. f, 19-apr-04 www.vishay.com 5 ordering information part number temperature range package SI9712dy SI9712dy-t1 ? 40 to 85 c soic-16 SI9712dy-t1?e3 truth table b s 1 s 2 s 3 s 4 switch 1 a switch 2 a switch 3 switch 4 switch 5 switch 6 0 0 0 0 off off off off on on 0 0 0 1 off off off on on off 0 0 1 0 off off on off on off 0 0 1 1 off off off off on on 0 1 0 0 off off off off on on 0 1 0 1 off on off on off off 0 1 1 0 off on on off off off 0 1 1 1 off off off off on on 1 0 0 0 off off off off on on 1 0 0 1 on off off on off off 1 0 1 0 on off on off off off 1 0 1 1 off off off off on on 1 1 0 0 off off off off on on 1 1 0 1 on off off on off off 1 1 1 0 on off on off off off 1 1 1 1 off off off off on on notes a. turn on of switch 1 and 2 are internally delayed until after v cc is valid. see figure 3. b. shaded lines are error conditions for pc card applications, however, switches default to the states shown. timing diagram s 1 s 2 figure 4. break-before-make of sw 1 and sw 2 v cc 0 +12 v in v pp
SI9712 vishay siliconix www.vishay.com 6 document number: 70024 s-40755?rev. f, 19-apr-04 typical characteristics (25 c unless otherwise noted) 0.00 0.02 0.04 0.06 0.08 0.10 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 0.00 0.02 0.04 0.06 0.08 0.10 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 0.0 0.1 0.2 0.3 0.4 0.5 0.00 0.04 0.08 0.12 0.16 0.20 0.00 0.05 0.10 0.15 0.20 0.25 ? 40 ? 20 0 20 40 60 80 100 120 0.00 0.02 0.04 0.06 0.08 0.10 ? 40 ? 20 0 20 40 60 80 100 120 0.0 0.1 0.2 0.3 0.4 0.5 0.00 0.05 0.10 0.15 0.20 0.25 0.30 switch 1?on-resistance vs. load current switch 2?on-resistance vs. load current on-resistance vs. junction t emperature on-resistance vs. junction t emperature i d ? load current (a) t j ? junction temperature ( c) t j ? junction temperature ( c) i d ? load current (a) switch 4?on-resistance vs. load current i d ? load current (a) ? on-resistance ( r ds(on) ) switch 3?on-resistance vs. load current i d ? load current (a) i d = 0.120 a switch 1 switch 2 switch 4 switch 3 i d = 1 a t j = t a t j = t a ? on-resistance ( r ds(on) ) ? on-resistance ( r ds(on) ) ? on-resistance ( r ds(on) ) ? on-resistance ( r ds(on) ) ? on-resistance ( r ds(on) )
SI9712 vishay siliconix document number: 70024 s-40755?rev. f, 19-apr-04 www.vishay.com 7 typical characteristics (25 c unless otherwise noted) 0 20 40 60 80 100 0 25 50 75 100 125 150 fall time (ms) 0 1 2 3 4 0 25 50 75 100 125 150 0 20 40 60 80 100 0 25 50 75 100 125 150 0 1 2 3 4 0 25 50 75 100 125 150 rise t ime vs. sr capacitor v alue fall time vs. sr capacitor v alue switch 3 rise time vs. load capacitance sr capacitor value (nf) c load ? load capacitance ( f) rise time (ms) c load ? load capacitance ( f) c load ? load capacitance ( f) sr capacitor value (nf) switch 3 fall time vs. load capacitance c load ? load capacitance ( f) rise time (ms) 0.1 1 10 100 1000 0.001 0.01 0.1 1 10 100 switch 3 switch 4 open open 0.1 1 10 100 100 0.1 1 10 100 fall time (ms) switch 3 switch 4 c sr = 33 nf fall time (ms) rise time (ms) switch 4 rise time vs. load capacitance switch 4 fall time vs. load capacitance c sr = 33 nf c sr = 33 nf c sr = 33 nf
document number: 91000 www.vishay.com revision: 18-jul-08 1 disclaimer legal disclaimer notice vishay all product specifications and data are subject to change without notice. vishay intertechnology, inc., its affiliates, agents, and employees, and all persons acting on its or their behalf (collectively, ?vishay?), disclaim any and all liability fo r any errors, inaccuracies or incompleteness contained herein or in any other disclosure relating to any product. vishay disclaims any and all li ability arising out of the use or application of any product describ ed herein or of any information provided herein to the maximum extent permit ted by law. the product specifications do not expand or otherwise modify vishay?s terms and conditions of purcha se, including but not limited to the warranty expressed therein, which apply to these products. no license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document or by any conduct of vishay. the products shown herein are not designed for use in medi cal, life-saving, or life-sustaining applications unless otherwise expressly indicated. customers using or selling vishay products not expressly indicated for use in such applications do so entirely at their own risk and agree to fully indemnify vishay for any damages arising or resulting from such use or sale. please contact authorized vishay personnel to obtain written terms and conditions regarding products designed for such applications. product names and markings noted herein may be trademarks of their respective owners.
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